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MC10EP195, MC100EP195 3.3V ECL Programmable Delay Chip
The MC10/100EP195 is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. http://onsemi.com The delay section consists of a programmable matrix of gates and multiplexers as shown in the logic diagram, Figure 2. The delay increment of the EP195 has a digitally selectable resolution of about MARKING DIAGRAM* 10 ps and a net range of up to 10.2 ns. The required delay is selected by the 10 data select inputs D[9:0] values and controlled by the LEN (pin 10). A LOW level on LEN allows a transparent LOAD mode of MCXXX real time delay values by D[9:0]. A LOW to HIGH transition on LEN EP195 will LOCK and HOLD current values present against any subsequent AWLYYWW changes in D[10:0]. The approximate delay values for varying tap 32 LQFP-32 numbers correlating to D0 (LSB) through D9 (MSB) are shown in FA SUFFIX Table 6 and Figure 3. 1 CASE 873A Because the EP195 is designed using a chain of multiplexers it has a fixed minimum delay of 2.2 ns. An additional pin D10 is provided for controlling Pins 14 and 15, CASCADE and CASCADE, also latched XXX = 10 or 100 by LEN, in cascading multiple PDCs for increased programmable A = Assembly Location WL = Wafer Lot range. The cascade logic allows full control of multiple PDCs. YY = Year Switching devices from all "1" states on D[0:9] with SETMAX LOW WW = Work Week to all "0" states on D[0:9] with SETMAX HIGH will increase the delay equivalent to "D0", the minimum increment. *For additional marking information, refer to Select input pins D[10:0] may be threshold controlled by Application Note AND8002/D. combinations of interconnects between VEF (pin 7) and VCF (pin 8) for LVCMOS, ECL, or LVTTL level signals. For LVCMOS input ORDERING INFORMATION levels, leave VCF and VEF open. For ECL operation, short VCF and See detailed ordering and shipping information in the package VEF (pins 7 and 8). For LVTTL level operation, connect a 1.5 V dimensions section on page 17 of this data sheet. supply reference to VCF and leave open VEF pin. The 1.5 V reference voltage to VCF pin can be accomplished by placing a 2.2 kW resistor between VCF and VEE for a 3.3 V power supply. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The 100 Series contains temperature compensation. * Maximum Input Clock Frequency >1.2 GHz Typical * Open Input Default State * Programmable Range: 0 ns to 10 ns * Safety Clamp on Inputs * Delay Range: 2.2 ns to 12.2 ns * A Logic High on the EN Pin Will Force Q to Logic Low * 10 ps Increments * D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL * PECL Mode Operating Range: Inputs VCC = 3.0 V to 3.6 V with VEE = 0 V * VBB Output Reference Voltage * NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.6 V
(c) Semiconductor Components Industries, LLC, 2004
1
October, 2004 - Rev. 13
Publication Order Number: MC10EP195/D
MC10EP195, MC100EP195
VEE D0 VCC Q Q VCC VCC NC
24 D1 D2 D3 VEE D4 D5 D6 D7 25 26 27 28 29 30 31 32 1
23
22
21
20
19
18
17 16 15 14 EN CASCADE CASCADE VCC SETMAX SETMIN LEN VEE
MC10EP195 MC100EP195
13 12 11 10 9
2
3
4
5
6
7
8
D8
D9 D10 IN
IN VBB VEF VCF
Figure 1. 32-Lead LQFP Pinout (Top View)
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MC10EP195, MC100EP195
Table 1. PIN DESCRIPTION
Pin 23, 25, 26, 27, 29, 30, 31, 32, 1, 2 3 4 5 6 7 8 9, 24, 28 Name D[0:9] I/O LVCMOS, LVTTL, ECL Input LVCMOS, LVTTL, ECL Input ECL Input ECL Input - - - - Default State Low Description Single-Ended Parallel Data Inputs [0:9]. Internal 75 kW to VEE. (Note 1) Single-Ended CASCADE/CASCADE Control Input. Internal 75 kW to VEE. (Note 1) Noninverted Differential Input. Internal 75 kW to VEE. Inverted Differential Input. Internal 75 kW to VEE and 36.5 kW to VCC. ECL Reference Voltage Output Reference Voltage for ECL Mode Connection LVCMOS, ECL, OR LVTTL Input Mode Select Negative Supply Voltage. All VEE Pins must be Externally Connected to Power Supply to Guarantee Proper Operation. (Note 2) Positive Supply Voltage. All VCC Pins must be externally Connected to Power Supply to Guarantee Proper Operation. (Note 2) Single-ended D pins LOAD / HOLD input. Internal 75 kW to VEE. Single-ended Minimum Delay Set Logic Input. Internal 75 kW to VEE. (Note 1) Single-ended Maximum Delay Set Logic Input. Internal 75 kW to VEE. (Note 1) Inverted Differential Cascade Output for D[10]. Typically Terminated with 50 W to VTT = VCC - 2 V. Noninverted Differential Cascade Output. for D[10] Typically Terminated with 50 W to VTT = VCC - 2 V. Single-ended Output Enable Pin. Internal 75 kW to VEE. No Connect. The NC Pin is Electrically Connected to the Die and "MUST BE" Left Open Noninverted Differential Output. Typically Terminated with 50 W to VTT = VCC - 2 V. Inverted Differential Output. Typically Terminated with 50 W to VTT = VCC - 2 V.
D[10] IN IN VBB VEF VCF VEE
Low Low High - - - -
13, 18, 19, 22
VCC
-
-
10 11 12 14 15 16 17 21 20
LEN SETMIN SETMAX CASCADE CASCADE EN NC Q Q
ECL Input ECL Input ECL Input ECL Output ECL Output ECL Input - ECL Output ECL Output
Low Low Low - - Low - - -
1. SETMIN will override SETMAX if both are high. SETMAX and SETMIN will override all D[0:10] inputs. 2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
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MC10EP195, MC100EP195
Table 2. CONTROL PIN
Pin EN State LOW (Note 3) Function Input Signal is Propagated to the Output
HIGH
LEN LOW (Note 3) HIGH SETMIN LOW (Note 3) HIGH SETMAX LOW (Note 3) HIGH D10 LOW (Note 3) HIGH
Output Holds Logic Low State
Transparent or LOAD mode for real time delay values present on D[0:10]. LOCK and HOLD mode for delay values on D[0:10]; further changes on D[0:10] are not recognized and do not affect delay. Output Delay set by D[0:10] Set Minimum Output Delay Output Delay set by D[0:10] Set Maximum Output Delay CASCADE Output LOW, CASCADE Output HIGH CASCADE Output LOW, CASCADE Output HIGH
3. Internal pulldown resistor will provide a logic LOW if pin is left unconnected.
Table 3. CONTROL D[0:10] INTERFACE VCF VCF
VCF VEF Pin (Note 4) No Connect 1.5 V $ 100 mV ECL Mode LVCMOS Mode LVTTL Mode (Note 5)
4. Short VCF (pin 8) and VEF (pin 7). 5. When Operating in LVTTL Mode, the reference voltage can be provided by connecting an external resistor, RCF (suggested resistor value is 2.2 kW $5%), between VCF and VEE pins.
Table 4. DATA INPUT ALLOWED OPERATING VOLTAGE MODE TABLE
CONTROL DATA SELECT INPUTS PINS (D [0:10]) POWER SUPPLY PECL Mode Operating Range NECL Mode Operating Range LVCMOS YES N/A LVTTL YES N/A LVPECL YES N/A LVNECL N/A YES
Table 5. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor ESD Protection (R1) Human Body Model Machine Model Charged Device Model Value 75 kW > 2 kV > 100 V > 2 kV Level 2 Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 in 1217 Devices
Moisture Sensitivity (Note 6) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 6. For additional information, see Application Note AND8003/D.
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IN R1 IN R1 EN R1 512 GD*
0 1 256 GD*
0 1 128 GD*
0 1 64 GD*
0 1 32 GD*
0 1 16 GD*
0 1 8 GD*
0 1 4 GD*
0 1 2 GD*
0 1 1 GD*
0 1 1 GD*
0 1
Q Q
MC10EP195, MC100EP195
Figure 2. Logic Diagram
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LEN R1 SET MIN SET MAX R1 10 BIT LATCH R1
5
VBB VCF VEF VEE
R1 D8
R1 D7
R1 D6
R1 D5
R1 D4
R1 D3
R1 D2
R1 D1
R1 D0
R1
D9
CASCADE Latch CASCADE
*GD = (GATE DELAY) APPROXIMATELY 10 ps DELAY PER GATE (MINIMUM FIXED DELAY APPROX. 2.2 ns)
D10
R1
MC10EP195, MC100EP195
Table 6. THEORETICAL DELAY VALUES
D(9:0) Value XXXXXXXXXX 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001000 0000010000 0000100000 0001000000 0010000000 0100000000 1000000000 1111111111 XXXXXXXXXX *Fixed minimum delay not included. SETMIN H L L L L L L L L L L L L L L L L L SETMAX L L L L L L L L L L L L L L L L L H Programmable Delay* 0 ps 0 ps 10 ps 20 ps 30 ps 40 ps 50 ps 60 ps 70 ps 80 ps 160 ps 320 ps 640 ps 1280 ps 2560 ps 5120 ps 10230 ps 10240 ps
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MC10EP195, MC100EP195
14000.0 13000.0 12000.0 11000.0 10000.0 9000.0 DELAY ( ps) 8000.0 7000.0 6000.0 5000.0 4000.0 3000.0 2000.0 1000.0 0.0 0.0 100.0 200.0 300.0 400.0 500.0 600.0 700.0 800.0 900.0 1000.0 VCC = 0 V VEE = -3.3 V 25C -40C 85C
Decimal Value of Select Inputs (D[9:0])
Figure 3. Measured Delay vs. Select Inputs
Table 7. MAXIMUM RATINGS
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJC Tsol Parameter Positive Mode Power Supply Negative Mode Power Supply Positive Mode Input Voltage Negative Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder 0 lfpm 500 lfpm Standard Board < 2 to 3 sec @ 248C LQFP-23 LQFP-23 LQFP-23 Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 6 -6 6 -6 50 100 0.5 -40 to +85 -65 to +150 80 55 12 to 17 265 Unit V V V V mA mA mA C C C/W C/W C/W C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
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MC10EP195, MC100EP195
Table 8. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 7)
-40C Symbol IEE VOH VOL VIH Characteristic Negative Power Supply Current Output HIGH Voltage (Note 8) Output LOW Voltage (Note 8) Input HIGH Voltage (Single-Ended) LVPECL LVCMOS LVTTL VIL Input LOW Voltage (Single-Ended) LVPECL LVCMOS LVTTL VBB VCF VEF VIHCMR IIH IIL ECL Output Voltage Reference LVTTL Mode Input Detect Voltage Reference Voltage for ECL Mode Connection Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 9) Input HIGH Current (@ VIH) Input LOW Current (@ VIL) IN IN 0.5 -150 1365 0 0 1790 1.4 1915 2.0 1890 1.5 2020 1690 800 800 1990 1.6 2120 3.3 150 0.5 -150 1430 0 0 1855 1.4 1940 2.0 1955 1.5 2080 1755 800 800 2055 1.6 2190 3.3 150 0.5 -150 1490 0 0 1915 1.4 1985 2.0 2015 1.5 2130 1815 800 800 2115 1.6 2265 3.3 150 mV V mV V mA mA 2090 2000 2000 2415 3300 3300 2155 2000 2000 2480 3300 3300 2215 2000 2000 2540 3300 3300 mV Min 100 2165 1365 Typ 145 2290 1490 Max 175 2415 1615 Min 100 2230 1430 25C Typ 150 2355 1555 Max 180 2480 1680 Min 100 2290 1490 85C Typ 150 2415 1615 Max 180 2540 1740 Unit mA mV mV mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -0.3 V. 8. All loading with 50 W to VCC - 2.0 V. 9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP195, MC100EP195
Table 9. 10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -3.3 V to -3.0 V (Note 10)
-40C Symbol IEE VOH VOL VIH VIL VBB VEF VIHCMR Characteristic Negative Power Supply Current Output HIGH Voltage (Note 11) Output LOW Voltage (Note 11) Input HIGH Voltage (Single-Ended) LVNECL Input LOW Voltage (Single-Ended) LVNECL ECL Output Voltage Reference Reference Voltage for ECL Mode Connection Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 12) Input HIGH Current (@ VIH) Input LOW Current (@ VIL) IN IN 0.5 -150 Min 100 -1135 -1935 -1210 -1935 -1510 -1385 -1410 -1280 Typ 145 -1010 -1810 Max 175 -885 -1685 -885 -1610 -1310 -1180 0.0 Min 100 -1070 -1870 -1145 -1870 -1445 -1360 -1345 -1220 25C Typ 150 -945 -1745 Max 180 -820 -1620 -820 -1545 -1245 -1110 0.0 Min 100 -1010 -1810 -1085 -1810 -1385 -1315 -1285 -1170 85C Typ 150 -885 -1685 Max 180 -760 -1560 -760 mV -1485 -1185 -1035 0.0 mV mV V Unit mA mV mV mV
VEE+2.0
VEE+2.0
VEE+2.0
IIH IIL
150 0.5 -150
150 0.5 -150
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -0.3 V. 11. All loading with 50 W to VCC - 2.0 V. 12. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP195, MC100EP195
Table 10. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 13)
-40C Symbol IEE VOH VOL VIH Characteristic Negative Power Supply Current Output HIGH Voltage (Note 14) Output LOW Voltage (Note 14) Input HIGH Voltage (Single-Ended) LVPECL CMOS TTL VIL Input LOW Voltage (Single-Ended) LVPECL CMOS TTL VBB VCF VEF VIHCMR IIH IIL ECL Output Voltage Reference LVTTL Mode Input Detect Voltage Reference Voltage for ECL Mode Connection Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 15) Input HIGH Current (@ VIH) Input LOW Current (@ VIL) IN IN 0.5 -150 1355 0 0 1775 1.4 1915 2.0 1875 1.5 2020 1675 800 800 1975 1.6 2120 3.3 150 0.5 -150 1490 0 0 1775 1.4 1940 2.0 1875 1.5 2080 1675 800 800 1975 1.6 2190 3.3 150 0.5 -150 1490 0 0 1775 1.4 1985 2.0 1875 1.5 2130 1675 800 800 1975 1.6 2265 3.3 150 mV V mV V mA mA 2075 2000 2000 2420 3300 3300 2075 2000 2000 2420 3300 3300 2075 2000 2000 2420 3300 3300 mV Min 100 2155 1355 Typ 135 2280 1480 Max 160 2405 1605 Min 100 2155 1355 25C Typ 140 2280 1480 Max 170 2405 1605 Min 100 2155 1355 85C Typ 145 2280 1480 Max 175 2405 1605 Unit mA mV mV mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 13. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -0.3 V. 14. All loading with 50 W to VCC - 2.0 V. 15. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP195, MC100EP195
Table 11. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -3.3 V (Note 16)
-40C Symbol IEE VOH VOL VIH VIL VBB VEF VIHCMR Characteristic Negative Power Supply Current (Note 17) Output HIGH Voltage (Note 18) Output LOW Voltage (Note 18) Input HIGH Voltage (Single-Ended) LVNECL Input LOW Voltage (Single-Ended) LVNECL ECL Output Voltage Reference Reference Voltage for ECL Mode Connection Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 19) Input HIGH Current (@ VIH) Input LOW Current (@ VIL) IN IN 0.5 -150 Min 100 -1145 -1945 -1225 -1945 -1525 -1385 -1425 -1280 Typ 135 -1020 -1820 Max 160 -895 -1695 -880 -1625 -1325 -1180 0.0 Min 100 -1145 -1945 -1225 -1945 -1525 -1360 -1425 -1220 25C Typ 140 -1020 -1820 Max 170 -895 -1695 -880 -1625 -1325 -1110 0.0 Min 100 -1145 -1945 -1225 -1945 -1525 -1315 -1425 -1170 85C Typ 145 -1020 -1820 Max 175 -895 -1695 -880 mV -1625 -1325 -1035 0.0 mV mV V Unit mA mV mV mV
VEE+2.0
VEE+2.0
VEE+2.0
IIH IIL
150 0.5 -150
150 0.5 -150
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 16. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -0.3 V. 17. Required 500 lfpm air flow when using +5 V power supply. For (VCC - VEE) > 3.3 V, 5 W to 10 W in line with VEE required for maximum thermal protection at elevated temperatures. Recommend VCC - VEE operation at 3.8 V. 18. All loading with 50 W to VCC - 2.0 V. 19. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP195, MC100EP195
Table 12. AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -3.6 V or VCC = 3.0 V to 3.6 V; VEE = 0 V (Note 20)
-40C Symbol fmax tPLH tPHL Characteristic Maximum Frequency Propagation Delay IN to Q; D(0-10) = 0 IN to Q; D(0-10) = 1023 EN to Q; D(0-10) = 0 D0 to CASCADE Programmable Range tPD (max) - tPD (min) Step Delay (Note 21) D0 High D1 High D2 High D3 High D4 High D5 High D6 High D7 High D8 High D9 High mono tSKEW ts Monotonicity (Note 27) Duty Cycle Skew (Note 22) |tPHL-tPLH| Setup Time D to LEN D to IN (Note 23) EN to IN (Note 24) th Hold Time LEN to D IN to EN (Note 25) tR Release Time EN to IN (Note 26) SET MAX to LEN SET MIN to LEN tjitter VPP tr tf RMS Random Clock Jitter @ 1.2 GHz Input Voltage Swing (Differential Configuration) Output Rise/Fall Time @ 50 MHz 20-80% (Q) 20-80% (CASCADE) 150 150 400 350 -25 200 275 3 800 1200 150 150 400 350 -75 250 200 3 800 1200 150 150 400 350 -50 300 225 3 800 1200 ps mV ps 85 100 100 140 135 200 85 110 110 150 135 200 95 130 125 170 155 220 200 400 60 250 200 400 100 280 200 400 80 300 ps 200 300 300 0 140 150 200 300 300 0 160 170 200 300 300 0 180 180 ps 25 25 25 ps 13 27 44 90 130 312 590 1100 2250 4500 14 30 47 97 140 335 650 1180 2400 4800 TBD ps 41 100 145 360 690 1300 2650 5300 1650 9500 1600 300 7850 2050 11500 2150 420 9450 2450 13500 2600 500 1800 10000 1800 350 8200 2200 12200 2300 450 10000 2600 14000 2800 550 1950 10800 2000 425 8850 2350 13300 2500 525 10950 ps 2750 15800 3000 625 ps Min Typ 1.2 Max Min 25C Typ 1.2 Max Min 85C Typ 1.2 Max Unit GHz ps
tRANGE Dt
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 20. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC - 2.0 V. 21. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range. 22. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output. 23. This setup time defines the amount of time prior to the input signal the delay tap of the device must be set. 24. This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than 75 mV to that IN/IN transition. 25. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response greater than 75 mV to that IN/IN transition. 26. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets the specified IN to Q propagation delay and transition times. 27. The monotonicity indicates the increasing delay value for each binary count increment on the control inputs D[9:0].
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MC10EP195, MC100EP195
IN VINPP = VIH(D) - VIL(D) IN Q VOUTPP = VOH(Q) - VOL(Q) Q tPHL tPLH
Figure 4. AC Reference Measurement
Cascading Multiple EP195s To increase the programmable range of the EP195, internal cascade circuitry has been included. This circuitry allows for the cascading of multiple EP195s without the need for any external gating. Furthermore, this capability requires only one more address line per added E195. Obviously, cascading multiple programmable delay chips will result in a larger programmable range: however, this increase is at the expense of a longer minimum delay.
Figure 5 illustrates the interconnect scheme for cascading two EP195s. As can be seen, this scheme can easily be expanded for larger EP195 chains. The D10 input of the EP195 is the CASCADE control pin. With the interconnect scheme of Figure 5 when D10 is asserted, it signals the need for a larger programmable range than is achievable with a single device and switches output pin CASCADE HIGH and pin CASCADE LOW. The A11 address can be added to generate a cascade output for the next EP195. For a 2-device configuration, A11 is not required.
ADDRESS BUS
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Need if Chip #3 is used
D7 D8 D9 D10 IN INPUT IN VBB VEF
D6
D5
D4
VEE
D3
D2
D1 VEE D0 VCC
D7 D8 D9 D10 IN IN VBB VEF
D6
D5
D4
VEE
D3
D2
D1 VEE D0 VCC
EP195
Q Q
EP195
Q OUTPUT Q
CHIP #2
VCC VCC CASCADE CASCADE
CHIP #1
VCC VCC CASCADE CASCADE
SETMAX
SETMIN
SETMIN
VCF LEN VEE
NC EN
VCF LEN VEE
SETMAX
NC EN
VCC
Figure 5. Cascading Interconnect Architecture
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VCC
MC10EP195, MC100EP195
An expansion of the latch section of the block diagram is pictured in Figure 6. Use of this diagram will simplify the explanation of how the cascade circuitry works. When D10 of chip #1 in Figure 5 is LOW this device's CASCADE output will also be low while the CASCADE output will be high. In this condition the SET MIN pin of chip #2 will be asserted HIGH and thus all of the latches of chip #2 will be reset and the device will be set at its minimum delay. Chip #1, on the other hand, will have both SET MIN and SET MAX deasserted so that its delay will be controlled entirely by the address bus A0--A9. If the delay needed is greater than can be achieved with 1023 gate delays (1111111111 on the A0--A9 address bus) D10 will be asserted to signal the need to cascade the delay to the next EP195 device. When D10 is asserted, the SET MIN pin of chip #2 will be deasserted and SET MAX pin asserted resulting in the device delay to be the maximum delay. Table 13 shows the delay time of two EP195 chips in cascade. To expand this cascading scheme to more devices, one simply needs to connect the D10 pin from the next chip to the address bus and CASCADE outputs to the next chip in the same manner as pictured in Figure 5. The only addition to the logic is the increase of one line to the address bus for cascade control of the second programmable delay chip.
TO SELECT MULTIPLEXERS
BIT 0 D0 Q0 LEN SET MIN SET MAX
Set Reset
BIT 1 D1 Q1 LEN
Set Reset
BIT 2 D2 Q2 LEN
Set Reset
BIT 3 D3 Q3 LEN
Set Reset
BIT 4 D4 Q4 LEN
Set Reset
BIT 5 D5 Q5 LEN
Set Reset
BIT 6 D6 Q6 LEN
Set Reset
BIT 7 D7 Q7 LEN
Set Reset
BIT 8 D8 Q8 LEN
Set Reset
BIT 9 D9 Q9 LEN
Set Reset
Figure 6. Expansion of the Latch Section of the EP195 Block Diagram
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MC10EP195, MC100EP195
Table 13. Delay Value of Two EP195 Cascaded
VARIABLE INPUT TO CHIP #1 AND SETMIN FOR CHIP #2 INPUT FOR CHIP #1 D10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 D8 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 D7 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 D6 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 D5 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 D4 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 D3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 D1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 1 D0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 Delay Value 0 ps 10 ps 20 ps 30 ps 40 ps 50 ps 60 ps 70 ps 80 ps 160 ps 220 ps 640 ps 1280 ps 2560 ps 5120 ps 10230 ps Total Delay Value 4400 ps 4410 ps 4420 ps 4430 ps 4440 ps 4450 ps 4460 ps 4470 ps 4480 ps 4560 ps 4720 ps 5040 ps 5680 ps 6960 ps 9520 ps 14630 ps
VARIABLE INPUT TO CHIP #1 AND SETMAX FOR CHIP #2 INPUT FOR CHIP #1 D10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 D8 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 D7 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 D6 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 D5 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 D4 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 D3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 D1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 1 D0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 Delay Value 10240 ps 10250 ps 10260 ps 10270 ps 10280 ps 10290 ps 10300 ps 10310 ps 10320 ps 10400 ps 10560 ps 10880 ps 11520 ps 12800 ps 15360 ps 20470 ps Total Delay Value 14640 ps 14650 ps 14660 ps 14670 ps 14680 ps 14690 ps 14700 ps 14710 ps 14720 ps 14800 ps 14960 ps 15280 ps 15920 ps 17200 ps 19760 ps 24870 ps
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MC10EP195, MC100EP195
Multi-Channel Deskewing
The most practical application for EP195 is in multiple channel delay matching. Slight differences in impedance and cable length can create large timing skews within a high-speed system. To deskew multiple signal channels, each channel can
be sent through each EP195 as shown in Figure 7. One signal channel can be used as reference and the other EP195s can be used to adjust the delay to eliminate the timing skews. Nearly any high-speed system can be fine-tuned (as small as 10 ps) to reduce the skew to extremely tight tolerances.
EP195
IN IN #1
Q Q
EP195 IN IN #2 Q Q
EP195 IN IN #N Control Logic Digital Data Q Q
Figure 7. Multiple Channel Deskewing Diagram Measure Unknown High Speed Device Delays
EP195s provide a possible solution to measure the unknown delay of a device with a high degree of precision. By combining two EP195s and EP31 as shown in Figure 8, the delay can be measured. The first EP195 can be set to SETMIN and its output is used to drive the unknown delay device, which in turn drives the input of a D flip-flop of EP31. The second EP195 is triggered along with the first EP195 and its output provides a clock signal for EP31. The programmed delay of the second EP195 is varied to detect the output edge from the unknown delay device.
CLOCK CLOCK EP195 IN IN #1 Q Q
If the programmed delay through the second EP195 is too long, the flip-flop output will be at logic high. On the other hand, if the programmed delay through the second EP195 is too short, the flip-flop output will be at a logic low. If the programmed delay is correctly fine-tuned in the second EP195, the flip-flop will bounce between logic high and logic low. The digital code in the second EP195 can be directly correlated into an accurate device delay.
Unknown Delay Device D EP31 Q
EP195 IN IN #2 Q Q
CLK
Q
Control Logic
Figure 8. Multiple Channel Deskewing Diagram
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MC10EP195, MC100EP195
Zo = 50 W
Q Driver Device Q
D Receiver Device
Zo = 50 W 50 W 50 W
D
VTT VTT = VCC - 2.0 V
Figure 9. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device MC10EP195FA MC10EP195FAR2 MC100EP195FA MC100EP195FAR2 Package LQFP-32 LQFP-32 LQFP-32 LQFP-32 Shipping 250 Units / Tray 2000 / Tape & Reel 250 Units / Tray 2000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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17
MC10EP195, MC100EP195
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1642/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC10EP195, MC100EP195
PACKAGE DIMENSIONS
32 LEAD LQFP CASE 873A-02 ISSUE B
-T-, -U-, -Z- AE P V AE
8 17
A
32
4X 25
A1
0.20 (0.008) AB T-U Z
1
-T- B B1 DETAIL Y
-U-
V1
DETAIL Y
BASE METAL
N -Z- 9 S1 S
8X 4X
F
D
M_ R
J
G -AB-
SEATING PLANE
DETAIL AD CE
SECTION AE-AE
-AC- 0.10 (0.004) AC 0.250 (0.010) H W X DETAIL AD
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC _ 1 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC _ 1 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
K
Q_
GAUGE PLANE
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
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19
0.20 (0.008)
0.20 (0.008) AC T-U Z
EE EE EE
9
M
AC T-U Z
MC10EP195, MC100EP195
ECLinPS is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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MC10EP195/D

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